Subventions et des contributions :

Subvention ou bourse octroyée s'appliquant à plus d'un exercice financier (2017-2018 à 2018-2019).

Analog-to-digital converters (ADCs) play a critical role in almost every aspect of our life. Various architecturesx000D
of ADCs are available. Among them, flash, delta-sigma, and successive approximation register (SAR) ADCsx000D
emerged as dominant architectures. Flash ADCs offer the highest conversion rate and are widely popular inx000D
applications such as high-speed data communications over wire and optical channels. The exponentially risingx000D
silicon area and power consumption with bit resolution and difficulties in combating comparator mismatchx000D
limit their resolution to no more than 6 bits. Delta-sigma ADCs achieve the highest resolution by means ofx000D
oversampling and noise-shaping. These ADCs are effective if signal bandwidth is small. SAR ADCs,x000D
introduced in 1950s and sat its debut in CMOS in 1970s, has played a significant role in advancing thex000D
state-of-the-art in ADCs since their inception. Although popular in telephony and low-speed instruments priorx000D
to the turning of 20th century, SAR ADCs have re-established themselves as the most promising ADCx000D
architecture inherently crafted for modern CMOS technologies with emerging applications ranging fromx000D
biomedical implants where power consumption is most critical to high-speed data links where conversion ratex000D
is pivotal, accredited to their compatibility with technology scaling. The key functional block of SAR ADCs isx000D
a digital-to-analog converter realized using capacitor arrays. At high conversion rates, the dynamic powerx000D
consumption of the capacitor arrays becomes prohibitively large. The silicon area needed to realize capacitorx000D
arrays also rises exponentially with bit resolution. Recently the feasibility of deploying time-mode techniquesx000D
in SAR ADCs was explored. As compared with SAR ADCs with binary-weighted capacitor arrays, time-modex000D
SAR ADCs offer the possibility of eliminating capacitor arrays so as to drastically lower power consumptionx000D
and silicon area. The objective of this project is to develop and prototype an 8-bit 1 GS/s SAR ADC using ax000D
time-mode approach.