Subventions et des contributions :

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Titre :

Latency-optimized SDN in wide area networks

Numéro de l’entente :

CRDPJ

Valeur d'entente :

164 000,00 $

Date d'entente :

14 juin 2017 -

Organisation :

Conseil de recherches en sciences naturelles et en génie du Canada

Location :

Ontario, Autre, CA

Numéro de référence :

GC-2017-Q1-00304

Type d'entente :

subvention

Type de rapport :

Subventions et des contributions

Informations supplémentaires :

Subvention ou bourse octroyée s'appliquant à plus d'un exercice financier. (2017-2018 à 2020-2021)

Nom légal du bénéficiaire :

Khisti, Ashish (University of Toronto)

Programme :

Subventions de recherche et développement coopérative - projet

But du programme :

Software Defined Wide Area Networks (SD-WAN) is one of the fastest growing markets in enterprise networks. By creating a logical overlay to intelligently route data across multiple paths, SD-WAN technologies provide higher capacities, lower costs and a simplified infrastructure to meet the ever increasing traffic demands. Many analysts predict that 2016 will be a breakout year for SD-WAN adaptation and implementation. The proposed project will make a fundamental contributions to SD-WANs by developing a new architecture to support applications with stringent latency constraints.x000D
Latency-optimization is a critical requirement for delay-sensitive applications such as interactive conferencing and desktop sharing, as well as cyber-physical systems and the Internet of Things. Such applications must compete with traffic generated from other sources including repair/maintenance applications or other delay tolerant applications in the backbone network. Furthermore in many real-world applications, packet retransmission have to be disabled and Forward Error Correction (FEC) must be used to avoid round-trip propagation delays. To address these challenges, the proposed research will develop a novel SD-WAN solution with integrated Forward Error Correction (FEC) for minimizing end-to-end latencies for delay sensitive applications.x000D
The proposed research will lead to the first fully functional FEC integrated SD-WAN that makes joint decisions on error correction and network path selection for latency optimization. On the theory side we will design new delay-sensitive FECs that can be seamlessly integrated into the SD-WAN configurations, as well as novel controller-algorithms for large scale networks with multiple flows. On the practical side we will implement software-based routers and high-performance controllers that can scale to heavy traffic volumes with tens of thousands of flows, perform query and update operations at line-speeds (Gbps), and use cross-layer network state information from the viewpoint of minimizing latency.x000D
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