Subventions et des contributions :

Subvention ou bourse octroyée s'appliquant à plus d'un exercice financier. (2017-2018 à 2022-2023)

Reconfigurable computing architectures, such as FPGAs (Field Programmable Gate Arrays), are enjoying a widespread renaissance, particularly in the lucrative cloud computing market. FPGAs are application-specific computing chips that allow implementation of circuits that are fully tailored to a specific problem, resulting in high performance and improved energy efficiency. Software companies like Microsoft have integrated FPGAs into their data center services through the highly influential Catapult project that uses FPGAs for accelerating both computations and network processing. Hardware manufacturers like Intel have developed new computing chips for these markets that combine processors and FPGAs.

Though FPGAs offer many advantages, they present significant challenges. Unlike software programming, FPGAs require compiling programs into low-level circuits. This requires a time-consuming, complex compilation flow built on heuristics which juggles conflicting metrics i.e. chip area, circuit speed, and power. It is not uncommon for an FPGA compilation (CAD) of a large design to take hours or even days while still not delivering the desired metrics. Industrial developers spend multiple man-months to ensure that the design meets these metrics.

A key goal of this proposal is to apply machine learning techniques to improve the quality and speed of hardware design process. This approach is in stark contrast with existing algorithms and heuristics that have delivered negligible improvements over the past few years. Instead of attempting to design generic algorithms, we will learn from a repository of knowledge about circuit patterns and their complex interactions with the FPGA CAD flow. We will generate this knowledge by evaluating the CAD tools in parallel through variations in their input configurations across different benchmarks. Additionally, we will build high-quality predictive models through this learning-driven approach to make better mapping decisions at various stages of the compilation flow.

In this proposal, we will also use machine learning to tackle reliability issues such as chip failures in the field due to external effects or manufacturing defects. To do this, we need to develop a new set of online (runtime) algorithms to monitor and adjust the circuits to respond to dynamic events. Instead of using pre-determined strategies, we will embed intelligence within the hardware to self-monitor and self-adapt to changing conditions. A learning-driven approach provides the hardware with the ability to respond to unforeseen events and conditions that cannot be exhaustively replicated in the testing labs.

The HQP trained through this program will acquire a blend of unique skills combining machine learning, hardware design, as well as software engineering. This is in high demand in the booming artificial intelligence and hardware design sectors of the Canadian industry.