Subventions et des contributions :

Titre :
Hardware Implementation of Cryptographic Algorithms on FPGAs and ASICs
Numéro de l’entente :
EGP
Valeur d'entente :
25 000,00 $
Date d'entente :
20 sept. 2017 -
Organisation :
Conseil de recherches en sciences naturelles et en génie du Canada
Location :
Ontario, Autre, CA
Numéro de référence :
GC-2017-Q2-04326
Type d'entente :
subvention
Type de rapport :
Subventions et des contributions
Informations supplémentaires :

Subvention ou bourse octroyée s'appliquant à plus d'un exercice financier (2017-2018 à 2018-2019).

Nom légal du bénéficiaire :
Areibi, Shawki (University of Guelph)
Programme :
Subventions d'engagement partenarial pour les universités
But du programme :

In recent times the ability to securely store and transfer critical data and sensitive information has proved ax000D
critical factor in success of business. In this age of universal electronic connectivity, of hackers, Trojans,x000D
viruses and electronic fraud, there is an important need for security and encryption.x000D
The most widely used symmetric encryption algorithms are 3DES, RC4, Twofish and AES.x000D
Examples of algorithms used in Asymmetric encryption are RSA, XTR and Diffie-Hellman.x000D
All the above mentioned algorithms can be implemented in either software or hardware. Hardware accelerationx000D
is the use of hardware to perform a task more efficiently than is possible in software. In order to achieve higherx000D
performance in today's heavily loaded communication networks, utilization of hardware accelerators forx000D
cryptography algorithms is more efficient. These hardware accelerators tend to offload the most computingx000D
intensive operations of encryption algorithms from the main processor.x000D
Reconfigurable logic allows the definition of new functions to be defined in hardware units, combiningx000D
hardware speed and efficiency, with ability to adapt and cope in a cost effective way with expandingx000D
functionality, changing environmental requirements, improvements in system features, changing protocols andx000D
data-coding standards.x000D
This proposal will perform architecture exploration to find efficient architectures for encryption algorithms.x000D
During the exploration phase, several architectures will be generated and evaluated to estimate the conflictingx000D
constraints and objectives such as area, performance, power consumption and flexibility.