Subventions et des contributions :

Subvention ou bourse octroyée s'appliquant à plus d'un exercice financier (2017-2018 à 2020-2021).

Information and Communication Technology (ICT) is currently experiencing significant mutations that will modify our interactions with electronics. Computing systems are expected to emerge with viable solutions for large, heterogeneous and unstructured data processing. Since conventional systems are fundamentally not adapted to this class of problem, alternative solutions are envisioned and demand a complete shift in the computing paradigm, architecture and technology. To this end, the bio-inspired computing model appears as a promising solution to conventional computing since these systems can manage multi-sensory inputs with very large bandwidth in real time and with low energy consumption. Along these lines, artificial neural networks have experienced renewed interest in recent years, outperforming humans in visual recognition tasks and gaming. Nevertheless, such systems would benefit immensely from a dense, parallel and distributed memory (synapses) along the computing nodes (neurons). We propose in this project to build an efficient and versatile system for the future development of machine learning hardware, and more precisely, we propose a scalable, flexible and innovative strategy for the implementation of the synaptic weight and the associated Multiply and ACcumulate operation (MAC), one of the most demanding resource for efficient ML hardware. x000D
We will capitalize on an ideal balance between CMOS performance and specific features available with emerging memory devices (i.e. synapses). HIDATA proposes two levels of integration: (i) we will use an advanced system-in-package approach in order to optimize heterogeneous integration of memory devices on CMOS chips. Here, we will design and fabricate memory chips interconnected via flip-chip technology on an active interposer which will ensure dynamic signal management and routing while minimizing memory device variability and preserving CMOS design flexibility. (ii) We will implement a massively parallel and dense memory array via multiple passive crossbar interconnection in a system-on-chip strategy. Active amplification between passive crossbars will enable ultra-high memory density while preserving optimal control of the memory devices.x000D
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